Recovery-Driven Design

This paper presents an error rate-optimal approach to reducing processor power whereby a processor is designed from the ground up to deliberately allow voltage overscaling-based timing errors during nominal operation, while a software or hardwarebased error resilience technique is used to tolerate these errors. This approach represents a shift from the traditional design philosophy of designing a processor core for correctness and then correcting any errors that occur under various operating conditions. We use our recovery-driven design methodology, in which a processors is optimized with an error resilience mechanism in mind, to optimize for Razor [2] hardware error tolerance and for error resilient applications [9]. We also show that a processor corelevel methodology can be used for the design of heterogeneously reliable multi-core processors, i.e., chip multiprocessor designs where different cores are power-optimized for different reliability targets. We show that recovery driven processors and heterogeneously reliable multi-core processors have substantial power benefits over their conventional single-core and multicore counterparts.